One example of an ESD protection circuit for integrated circuits is disclosed in JP 2003-124336 A. According to the configuration disclosed in JP 2003-124336 A, a passive element formed on the nonconductive layer below the bonding pad establishes connection between the bonding pad and the integrated circuit. Such configuration allows effective use of the chip surface and prevents functional degradation of the integrated circuit when mechanical stress is applied to the bonding pad. Also, a sizable resistive element occupies a large portion of the chip surface in order to impart appropriate ESD protection for CMOS circuit.
However, recent increase in memory capacity and device integration has lead to increase in static electricity charged in the semiconductor chip as compared with the conventional configuration. The technical idea of JP 2003-124336 A is to provide protection from device destruction caused by electro static discharge, thus, a large resistive element composed of electrode interconnect is employed. However, resistive element alone merely provides reduction of electro static charge owning to voltage drop attributable to resistance component (R). In order to improve ESD tolerance, reduction of RC product, the reduction of C component in particular, is required especially in charged device model (CDM). Thus, resistive element merely composed of electrode interconnect is insufficient for achieving such objective.